Modern integrated circuits (ICs) comprise a complex arrangement of components and electronic structures which are interconnected with one another in a plurality of planes arranged one above the other. The fabrication of such circuits constitutes a complicated sequence of different process steps. Inter alia, more than 25 different patterning steps have become necessary in the meantime in the fabrication of specific circuits.
As a reaction to the demand for ever faster and more expedient integrated circuits, the semiconductor industry is always endeavoring to realize ever smaller circuit dimensions. Again and again more complex fabrication processes are developed in the course of this, said processes permitting a higher integration density. However, the increase in the integration density and the reduced feature sizes associated therewith are also accompanied by an increase in the requirements made of the precision of the processes used.
One of the most important processes and one which is carried out the most often in semiconductor fabrication is the photolithographic patterning process, in which a structure arranged on an exposure mask is transferred into a photoresist layer, applied to the wafer surface beforehand, by means of an exposure unit and subsequent selective etching. In this case, what is particularly important is the accurate overlay of the transferred structure with structures that are already present on the wafer surface. Thus, even small overlay errors (center position errors) of structures produced in different steps may prove to be extremely critical with regard to the functionality of a large scale integrated circuit. Therefore, the overlay is accorded one of the key roles in the modern semiconductor process with regard to performance and yield.
However, the overlay also plays an important role with regard to the integration density itself. Generally, in the case of integrated circuits, the so-called relative center position error of two structures arranged one above the other (such as e.g. interconnect and contact hole) is permitted to exceed not more than about one third of the minimum structure if the intention is to fully utilize the packing density that is possible with the minimum structure.
In order to reduce the center position error, it is necessary to orient the semiconductor wafers as accurately as possible within the corresponding devices. This orientation operation is called alignment. The alignment operation in an exposure device of a photolithography installation for the accurate overlay of a mask structure with a structure that is already present on the wafer is composed of three individual steps: first of all, it is necessary to identify suitable alignment marks on the wafer surface. This is generally done with the aid of a light-optical microscope (alignment microscope), an optical parameter of a light reflected from the wafer surface being evaluated by eye or automatically. Afterward, it is necessary to determine the positional error of the alignment marks relative to the alignment microscope or relative to the mask. Finally, in order to correct the relative positional error, it is necessary to execute relative movements between wafer and alignment microscope or mask.
The determination of the alignment mark position takes place with the aid of known optical methods which, depending on the alignment mark, can supply a contrast between different regions of the alignment mark. In particular, the edge contrast, phase contrast, diffraction contrast or Fresnel zone method is taken into consideration in this case. None of these methods is unproblematic, however, because the contrast of the alignment marks which is used for position determination depends on the surface constitution of the measurement object (e.g. layer thicknesses, surface roughness and/or edge profile of the alignment mark). However, the surface constitution of the alignment marks generally depends on the fabrication process respectively used. The dictates of the process mean that the structures of the alignment marks therefore often have profile fluctuations which do not permit any accurate determination of the alignment mark position and thus the accurate alignment of the wafer with the aid of the methods used for this purpose heretofore.